The global chip shortage dominates the news and the semiconductor industry worries. Even consumers who thought nothing about what powers their mobile devices understand the next model may be years away due to the shortage.
One workable way out of the shortage is to reuse existing field programmable gate array (FPGA) designs with today’s technology and Lanza techVentures portfolio company Plunify could just be part of that solution. Its design software, in use at various systems companies developing FPGAs, optimizes a design’s performance and eliminates many performance deficiencies.
Plunify, the name a combination of programmable logic (PL) and unify, was founded in 2009 by Harnhua Ng and Kirvy Teo who understand the challenges confronting FPGA engineers using vendor-specific design tools. They identified a way to compile and optimize register transfer level (RTL) code for an FPGA application using powerful, machine learning algorithms. The tool called InTime applies synthesis and place and route (P&R) technology to analyze design data and optimize it for better performing FPGA designs.