Inventions and Patents

While Lucio Lanza may be better known within the semiconductor industry as an early-stage investor and Managing Director of Lanza techVentures, he has distinguished himself equally as an inventor and patent holder.

Early patents were granted to him and Olivetti colleagues by the United States Patent and Trademark Office (USPTO) for memory controller devices in the 1970s, the early days of the semiconductor revolution. Later, he and a colleague at Gradient Design Automation (now Keysight Technologies, NYSE: KEYS) were granted two patents in 2005 and 2007 for methods used for thermal testing of chips. Lucio and colleagues from Fabbrix (now PDF Solutions, Inc., Nasdaq: PDFS) were awarded two patents in 2008 and 2006 for methods and processes for chip design using geometric patterns. Two additional patents were awarded in 2007 and 2011 to Lucio and colleagues at PDF Solutions.

Patent No. US-7906254-B2: Method and Process for Design of Integrated Circuits Using Regular Geometry Patterns to Obtain Geometrically Consistent Component Features

Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit. Filed: March 15, 2011
Date of Patent: October 2, 2007
Assignee: PDF Solutions, Inc., San Jose, CA (US)
Inventors: Lawrence T. Pileggi, Andrzej J. Strojwas, Lucio L. Lanza
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Application No. US-20080098334-A1: Method and Process for Design of Integrated Circuits Using Regular Geometry Patterns to Obtain Geometrically Consistent Component Features

Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.
Filed: October 2, 2007
Publication date: April 24, 2008
Inventors: Lawrence Pileggi, Andrzej Strojwas, Lucio Lanza
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Patent No. US-7278118-B2: Method and Process for Design of Integrated Circuits Using Regular Geometry Patterns to Obtain Geometrically Consistent Component Features

Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.
Filed: November 4, 2005
Date of Patent: October 2, 2007
Assignee: PDF Solutions, Inc., San Jose, CA (US)
Inventors: Lawrence T. Pileggi, Andrzej J. Strojwas, Lucio L. Lanza
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Patent No. US-7191413-B2: Method and Apparatus for Thermal Testing of Semiconductor Chip Designs

Abstract: A method and apparatus for thermal testing of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and positioning temperature sensors within a corresponding semiconductor chip in accordance with the calculated full-chip temperatures (e.g., in the regions of steep thermal gradients). Thus, temperature sensors are strategically placed in the regions where they are most likely to be needed, according to calculated temperatures, rather than randomly positioned throughout a test chip.
Filed: March 11, 2005
Date of Patent: March 13, 2007
Assignee: Gradient Design Automation, Inc.
Inventors: Rajit Chandra, Lucio Lanza
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Application No. US-20060112355-A1: Method and Process for Design of Integrated Circuits Using Regular Geometry Patterns to Obtain Geometrically Consistent Component Features

Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.
Filed: November 4, 2005
Publication date: May 25, 2006
Applicant: Fabbrix, Inc.
Inventors: Lawrence Pileggi, Andrzej Strojwas, Lucio Lanza
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Application No. US-20050166166-A1: Method and Apparatus for Thermal Testing of Semiconductor Chip Designs

Abstract: A method and apparatus for thermal testing of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and positioning temperature sensors within a corresponding semiconductor chip in accordance with the calculated full-chip temperatures (e.g., in the regions of steep thermal gradients). Thus, temperature sensors are strategically placed in the regions where they are most likely to be needed, according to calculated temperatures, rather than randomly positioned throughout a test chip.
Filed: March 11, 2005
Publication date: July 28, 2005
Inventors: Rajit Chandra, Lucio Lanza
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Patent No. US-4156290-A: Speedup Addressing Device by Detecting Repetitive Addressing

Abstract: A memory addressing device for a memory divided in a plurality of elements each storing a plurality of information words. Each address for the memory comprises a first part which controls addressing means which address all the words of the memory elements stored in the address identified by said first part. All the addressed words are stored in corresponding output registers of the memory elements. The second part of the address enables the selection of the output register associated therewith. Consequently the reading operation for a block of information requires only one memory access time plus the read time of the output registers.
Filed: August 26, 1976
Date of Patent: May 22, 1979
Assignee: Ing. C. Olivetti & C., S.p.A.
Inventor: Lucio Lanza
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Patent No. US-4032895-A: Electronic Data Processing Computer

Abstract: An electronic computer comprising a first memory for recording instructions and data to be processed, a second memory for recording microinstructions and addressable by the instructions to provide a succession of microinstructions which is associated with each of the instructions and a third memory for recording a plurality of words and addressable by the microinstructions to provide at least one word associated with each of the microinstructions. Operation control means and a plurality of registers connectable to the control means and to the memories are provided for processing the data and two groups of signals are included in the words for controlling the operations of the control means and the registers. The control means and the registers are directly supplied with the signals of the first group for selecting the operations to be performed according to the signals of the first group.
Filed: August 14, 1975
Date of Patent: June 28, 1977
Assignee: Ing. C. Olivetti & C., S.p.A.
Inventors: Lucio Lanza, Francesco Giovanni Vecchio
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